`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/12/28 19:52:57
// Design Name: 
// Module Name: cordic_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module cordic_tb;
logic        clk;
logic        rst_n;
logic        start;
logic [31:0] theta;
logic [31:0] v_cos;
logic [31:0] v_sin;
logic        done;
//
initial begin
    clk = 1'b0;
    forever begin
        #5 clk = ~clk;
    end
end
initial begin
    rst_n = 1'b0;
    #100
    rst_n = 1'b1;
end
//
initial begin
    start = 1'b0;
    theta = 'd0;
    #202
    theta = $signed(30);
    start = 1'b1;
    #10
    start = 1'b0;
    #200
    theta = $signed(45);
    start = 1'b1;
    #10
    start = 1'b0;
    #200
    theta = $signed(60);
    start = 1'b1;
    #10
    start = 1'b0;
end

assign theta = $signed(30);
//
cordic cordic_inst(
    .clk  (clk  ),
    .rst_n(rst_n),
    .start(start),
    .theta(theta),               //0<theta<90
    .v_cos(v_cos),
    .v_sin(v_sin),
    .done (done )
);
endmodule
